1. Field of the Invention
This invention relates generally to a testing integrated circuit for testing a logical integrated circuit, and more particularly to a testing integrated circuit which can easily perform parametric test by means of a simple custom-designed test apparatus.
2. Description of the Related Art
As disclosed in U.S. Pat. No. 4,749,947, a testing integrated circuit for testing functions of an IC chip has been developed in various fashions, and the size of a test structure has been increased as functions of an IC chip become more complicated.
A test structure and method called boundary-scan are known, by which a large scale digital system including a plurality of IC chips having number of input and output pins can be tested easily. A basic concept of the boundary-scan-testing is disclosed in U.S. Pat. No. 3,790,885. Nowadays a digital microcircuit device has a great number of signal lines, which increases the cost of a system to test it. The boundary-scan testing is an effective technique to overcome this problem.
A boundary-scan-testing device has the following structure, for example. A peripheral cell area of an IC chip includes memory circuits for use in test, each connected to a signal line connected to an external terminal. The memory circuits are connected each other to constitute a shift register serving as a testing structure. With such IC chips mounted on a board, a functional test is performed by utilizing the testing structure. Each of the IC chips has a data input terminal, a data output terminal, and a test control terminal. The terminals of the IC chips are connected so as to perform a desired test. Data for use in a test is serially input through the data input terminal of an IC chip, subjected to a serial shift operation by a control signal, and serially output through the data output terminal. In this manner, data can be written in and read out from memory circuits. In other words, the serial shift operation of the test data allows an individual test for each of the IC chips.
The boundary-scan-testing is advantageous not only in the functional test performed independently for each of the IC chips on the board, but also in an inspection of preparation for delivery of semiconductor devices including IC chips. More specifically, a boundary-scanning structure such as memory circuits arranged to form a shift register incorporated in an IC chip is utilized to inspect a semiconductor device. The inspection is effective particularly in testing a logic device having a plurality of pins, which requires data to be input through a number of input terminals thereof. Since, in boundary-scan testing, a test data can be supplied to an IC chip by a serial test data operation, a functional test can be performed by a custom-designed test apparatus having a small number of pins. These test technique contribute to unacceptable increase of high pin count device's testing cost.
However, the conventional structure for boundary-scan-testing cannot perform a parametric test on peripheral cells in an IC chip. A parametric test is an indispensable item in an inspection of preparation for delivery. In the parametric test, electric characteristics (e.g., input and output current characteristics) of peripheral cells such as input and output buffers, provided on the periphery of a logic device, are tested.
In the conventional boundary-scan-testing structure, only the data input terminal, the data output terminal, and the test terminal for supplying a control signal are connected to a custom-made test apparatus. Hence, a parametric test cannot be performed for every input and output buffers provided on the periphery of the logic device.
As described above, in an IC chip having a structure for boundary-scan-testing according to the conventional art, although a functional test can be performed by a serial operation, a parametric test cannot be performed for the peripheral cells such as every input and output buffers without boundary-scan test terminals provided in the peripheral area of the IC chip.